1. Field of the Invention
The present invention is directed generally toward a method and apparatus for forcing bus formats. More specifically, the present invention is directed to forcing bus configurations of a Peripheral Component Interconnect (PCI) device.
2. Discussion of Related Art
As technology in the field of microprocessors progresses, capabilities of microprocessors to handle more data increase. Typical microprocessors presently operate on 64 bits of parallel data or greater. Many microprocessors are used in systems that include and communicate with other devices via interface buses. Peripheral Component Interconnect (PCI) is one common interface bus frequently used in such systems. As used herein, a PCI device is a device capable of being coupled to a PCI bus.
PCI devices are typically connected to a PCI bus on a motherboard with pin connectors, commonly referred to as “sockets” or “edge connectors”. However, those skilled in the art will recognize that a PCI device may also be directly coupled to a PCI bus without a need for a pin connector. A microprocessor typically connected to the motherboard communicates with the PCI devices through the PCI bus. The PCI bus includes a number of parallel data lines for transferring data and control signal between PCI devices. For example, a microprocessor that is capable of processing 64 bits of data can transfer 64 bits of data to a PCI device through a PCI bus that has 64 lines, provided that the PCI device is also capable of processing such data. Such a data bus is appropriately called a 64-bit PCI bus. Similarly, PCI devices can transfer 64 bits of data to the microprocessor through the 64-bit PCI bus.
PCI device technology advancements have maintained a corresponding pace with microprocessor technology advancements. However, a problem occurs when a PCI device is connected to a data bus that is incapable of transferring a required number of data bits from the PCI device. For example, a PCI device that is capable of transferring 64 bits of data will experience data errors when attempting to transfer 64 bits of data through a 32-bit PCI bus. While technology of PCI devices has progressed, many PCI devices are used to communicate through data buses that are incapable of transferring a higher number of data bits from the PCI devices.
PCI specifications have requirements that allow PCI devices to communicate the number of bits to be processed between a PCI device and a PCI bus. Bus-width control signals that include a request for communications and an acknowledgement of communications are transmitted to establish a bus-width for communications with respect to a number of bits. If the PCI device is to communicate through a PCI bus on a motherboard that transfers a lesser number of bits, PCI specifications require that a “pull-up” resistor be placed on the motherboard. The “pull-up” resistor pulls a voltage level for the request and the acknowledgement to a logical high, thereby formatting the bus and forcing the PCI device to transfer the lesser number of bits.
An example of PCI specifications is the PCI 2.2 specification. The PCI 2.2 specification requires that 32-bit connectors, such as 32-bit PCI card slots, have bus-formatting “pull-up” resistors to pull a request for 64-bit bus communications and/or an acknowledgement of 64-bit bus communications to logical 1. If the request for 64-bit bus communication is not pulled high, the request for 64-bit bus communication floats and potentially causes an improper request for 64-bit communications when 32-bit communications are desired and/or necessary. An acknowledgement of 64-bit communications acts in a similar manner.
Many legacy motherboards have PCI bus systems designed for 32-bit communications that pre-date the PCI 2.2 specifications. PCI 2.2 specifications require that PCI buses employ the bus-formatting “pull-up” resistors when a 32-bit bus interfaces with a 64-bit PCI device. Legacy motherboards are considered to be non-compliant or non-compatible when the legacy motherboards do not meet the PCI 2.2 specifications. Placing the bus-formatting “pull-up” resistors on a PCI device violates the PCI 2.2 specifications. Alternatively, permanently forcing the request for 64-bit bus communications and/or the acknowledgement of 64-bit bus communications to a logical 1 would force a PCI device to permanently operate as a 32-bit PCI device. Permanently operating the 64-bit PCI device as a 32-bit PCI device precludes a future use as a 64-bit PCI device. Therefore, a device is needed to control the number of bits to be transferred from the PCI device through a PCI bus. The device should also comply with both present and past PCI specifications relating to an existence and a location of “pull-up” resistors.